Stupid `include directive problem....

[jelydonut]

I've never had to do this before and now that I have to of course it turns in to a issue...

Im trying to make a .h file consisting of parameters which I can just `include at compile time. For some reason the parameters only seem to work if i just have them in the module itself..

any ideas?

jelydonut

 

[WA]

@jelydonut

It sounds like a multiple including. This usually causes errors so you might want to use an #ifndef statement.

I'm not sure if you have c++ book so I'll give example.

********Class File*******
#ifndef MyType_h
#define MyType_h
.
.
.
.
#endif
*******End Class File******

What this does is, if this class is included from a main function call (#include), the ifndef determines if it defined earlier.
If it was, don't re define. But if it wasen't, then continue to the end (#endif).

Hope this helps
WA

 

[yeewang]

Hi, WA, `include seems more like verilog, not C++

 

[WA]

yeewang quotes:

Hi, WA, `include seems more like verilog, not C++

It is my understanding that both languages are similar.
I'm not too familiar with the syntax of verilog though.

I believe that verilog and vhdl were deliberately made similar to c++.
I think this was done so we didn't have to learn a whole new language to programming whatever device we're using (ease of learning?).
But there is some differences though.

For example, if you look at a vhdl listing for an or-gate (or something similar), you will see that it looks like an sub-function in c++.

Again hope this helps.
WA

 

[jelydonut]

I was refering to Verilog.. I forgot to mention that..

It turns out though I was putting it below the `timescale directive.. and for a parameter to work it has to be located inside the module.. so once I moved it, it started working..

jelydonut