Stuck at fault & Memories testing

Hello,

I want detailed explanation about stuck-at fault method. I couldn't get the concept. I tried to learn on google. But I still don't get it.:???: I know! I'm not good at grasping things.:shock: A help in this concept is greatly appreciated.:-D I just need detailed explanation. If possible please give examples with explanations. Thanks in advance for your time.:razz:

Despite working in electronic maintenance for twenty years, I have never heard of it. From a brief look at the Wicki entry, I think it goes like this:- Suppose you are making a digital PCB which you then test on your ATE. Traditionally if a board failed it would be then passed to a manual testing section where the signal path would be traced through. With Stuck node analysis, during the programming of the ATE, each node (piece of wire joining inputs and outputs) would be artificially forced to 1 and a 0 and the results programmed into the ATE. So the ATE would report back the node number and its fault when a Board failed. this way PCB errors (solder splashes/hairline cracks) could be checked for by low grade staff and some times the correct ICs changed by wiremen. So the use of very expensive Engineers is minimised.
This looks like a poor mans signature analysis, for use on non computer based logic systems.
Frank

Stuck-at is one class of logical fault, and the one that has
the most mature fault-simulation tool coverage. The idea
simply is that, net by net, the value is forced and the
observability of that fault at any output is determined.
This is repeated for all nets (although, often only at
levels above the cell library primitive gate, which could
exhibit behaviors other than stuck-output as a result of
internal stuck-ness). You get a fault-coverage percent
which your "methodology harpies" will insist beats some
target.

Now there are also stuck-to, open, weak-drive-vs-tight-
timing type faults which the stuck-at scheme will not
emulate. But stuck-at is a good first pass at assuring
test coverage.