strong driver of zero and strong driver of one concepts in CMOS

can any one explain in clear about strong driver of zero and strong driver of one concepts in CMOS?

Hello,
CMOS main advantage is : pMOS pass strong 1 and weak 0 and nMOS pass strong 0 and weak 1

nMOS needs Vth to keep it in operating condition, there is a loss of Vth when logic '1' is passed. This loss makes the output to give weak '1'. In the same terminology, it passes strong '0'. In short, nmos can transfer any voltage from 0 to V1 strongly here V1 = Vip - Vth.
Same reason for pMOS.

prahullchintu said:

can any one explain in clear about strong driver of zero and strong driver of one concepts in CMOS?

Click to expand...

Basically, CMOS- "Complementary" defines the opposite behavior of pMOS and nMOS.

nMOS - works when input to gate is high
pMOS - works when input to gate is low.

The threshold is +ve for nMOS and -ve for pMOS.
The source of pMOS is connected to VDD and nMOS to VSS.

So, for nMOS when gate input is greater than threshold, and source is VSS the drain will be VSS. When Source is VDD the drain will VDD-Vth , hence it passes strong VSS(0).
Whereas, for nMOS when gate input is greater than threshold, and source is VDD the drain will be VDD. pMOS passes strong 1 (VDD)

Hope this helps

thanks for that can u make VERY clear explanation of it

prahullchintu said:

thanks for that can u make VERY clear explanation of it

Click to expand...

The important aspect to note here is the threshold voltage (of the transistor, which describes the voltage at which the transistor switches on and off (the on/off action of the transistor corresponds to the existence of the conducting transistor channel).

We know for nMOS transistors that the transistor is OFF when: Vgs<Vt

If Vgs>Vt then the nMOS transistor is ON.

For the pMOS transistor the voltages are expressed as negatives with respect to the nMOS voltage because of the opposing majority charge carriers in nMOS and pMOS transistors.

Therefore, for pMOS transistors the transistor is OFF when:

Vgs>Vt

However in pMOS calculations Vgs and Vt will be negative voltages. You can take the magnitudes and the rules for pMOS transistors will be the same as for nMOS; therefore for pMOS transistors the transistor is OFF when:

|Vgs|<|Vt|

Ok, so now we've cleared up the terminology and defined the above equations defining the switch on/off points consider a simple pMOS transistor with a voltage on the gate of 0 volts (a strong logic '0').

If the input is at VDD (a strong logic '1') which would be greater in magnitude than 0 volts, then:

|Vgs|=|Vdd| >|Vth|


The transistor will be switched on, and the input at VDD will be reflected at the output also as VDD, i.e. the output will be a strong logic '1'.

This illustrates the strong logic '1' output for a pMOS transistor.

Ok, lets look at the case for logic '0'.

If we start to reduce the input voltage from VDD to 0 volts, we get to a point where the input voltage will equal Vth .

When the input gets to Vth, then:

|Vgs|=|Vth|

And the transistor switches off - the conducting channel between the source and drain closes. At this point the voltage at the output is also Vth

Any further reductions in the input voltage will have no effect on the output voltage because the transistor is switched of by virtue of the fact that |Vgs|<|Vth|

This illustrates the weak logic '0' of the pMOS transistor - that is the output can never get down to 0 volts (the point of a strong logic '0') because the transistor switches off before the output can get that low.

thanks for ur explanation