stray inductances in parallel

[eem2am]

i am laying out pcb for SMPS 10 w (10v battery input).

the pcb is very small. It is difficult to cram all the components and get a small current loops everywhere...so to compensate i do lots of current loops in parallel because then the stray inductances in parallel get less overall stray inductance/

Is this so?

 

[FvM]

the pcb is very small

Generally the best way to achieve low inductance design

so to compensate i do lots of current loops in parallel

I don't understand, what you mean. Consider e.g. the commutating current loop of a buck converter. It is from ground through input capacitor, input switch and diode back to ground. How do split it into multiple current loops in parallel, exept for using multiple input capacitors and possibly two diodes instead of one, which is a common technique of course?

 

[eem2am]

thanks,

actually i was referring to the loops due to the fact that my controller IC's ground pin is being routed by several routes to the "general" ground plane which is copper poured between the components