strategy to find the setup/hold time values for a Flip-Flop

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rajsach13

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Hello !!

I would like to understand better the Standard Cell characterization step for a classic Flip-Flop without any Testability neither inverted Output.
Let's say in 40nm CMOS.

How is the setup/hold time computed, I mean what is the strategy to get the setup/hold time values in the .lib files ?
Does everything start from an initial range of setup coming from the Techno team, let's say for example : setup inside [20ps:120ps] for a FF drive X1 ? And then, does the characterization step will end to write in the .lib, the setup value such as the Q output gets well the D data input, the D data input being closer and closer to the clock rising edge (and so reducing the setup value)?

Thanks a lot for your help.

R.
 

The second part is correct, the FF is simulate with analog model, and the D CK are stimulate to reach the limit of the behavior, then some marge is added.
 

The setup/hold time calculation can be referred to report_delay_calculation during Design Compiler.
Basically, the tool will refer to the timing table provided by .lib and calculate the result with input clock transition.
 

Thanks !! Actually, analyzing your returns, I would like to get some more info regarding the/my extract : "the setup value such as the Q output gets well the D data input". What is the criteria ?? If D=1 and Q gets the 1 it sounds that the Data waveform can be closer to the CLK rising edge, to define the accurate setup time. However, I think, there should be some delay point also. I mean, I have heard somewhat, something linked to a CP to Q time constraint.

So, I think, the Q output should, indeed gets the D data input value just after the CLK rising edge, but within a defined delay, right ??

Thanks to provide me some help !!

R.
 

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