Strange wire names after using DC to synthesize Verilog file

[fantaci]

strange problem of DC

I encountered strange problem when using DC to synthesize my verilog source file. In my synthesized netlist, in some module a few wires’ name is very strange: \*cell*9614/U5/Z_0. To prevent DC from producing such strange wires’ name, I use some options in my DC script:
……
Define_name_rules my_name_rules –case_insensitive –restricted "/ \\ \*" –map {{"\*cell\*", "mycell"}}
Change_names_rules my_name_rules –hierarchy
……
But it still does not work.
I need help.

 

[cnz]

Re: strange problem of DC

try this below!


define_name_rules verilog -check_bus_indexing

change_names -rules verilog -hierarchy

set hdlout_internal_busses true
set bus_inference_style %s\[%d\]

 

[fantaci]

Re: strange problem of DC

It does not work

 

[cnz]

Re: strange problem of DC

Which version of DC which you used?