strange strcuture of EEPROM cell

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afujian

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Hi,Can anyone explain why there is a port PB connnect to the float gate through a MOS capacitor as shown in the EEPROM cell?
 

I'm guessing this represents some parasitics, is all.
Where those parasitics bleed / return charge to, is
going to affect read times and so on. It looks like a
pretty trivially-sized device and is only representing
some capacitance.

Sometimes you put those ports in for design purposes
(observability in simulation) and it's not worth the
time to take them back out just to not confuse others.
 

hi dick_freebird ,thanks for your reply,I'm afraid this does not represent the parasitic cap,because the data line from the control logic is connected to the port PB,so,this port may have some relationship with programming, is that possible?
 

Do you have the layout of this cell or program condition?
I guess that programming might be via pch5.
 

I think it could be a PRESET input. By applying a voltage step to VDD resp. to GND to this input, one can inject or remove a certain amount of charge to/from the gate, so generating a required preset condition.
 

sorry ,there's only schematic

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hi erikl ,the voltage of port PB has three values ,0 5V 15V respectively
 

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