mohmohcha
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Hi folks. I am designing a voltage doubler in a TSMC process. I used diode-connected native transistors (VTH is a few ten mV) and the schematic is shown in the enclosed pic.
When I did transient simulation, I found something weird and different to what I read. At the moment when the transistors were turned on/off, I saw some current spikes, see the fig.
I can reduce the amplitude of the spikes by
1) decrease the size of the transistors
2) Reduce the input signal frequency
This gives me the feeling the spikes are due to some capacitive divider, does anyone have any clue on this?
Thanks.
When I did transient simulation, I found something weird and different to what I read. At the moment when the transistors were turned on/off, I saw some current spikes, see the fig.
I can reduce the amplitude of the spikes by
1) decrease the size of the transistors
2) Reduce the input signal frequency
This gives me the feeling the spikes are due to some capacitive divider, does anyone have any clue on this?
Thanks.