lhlbluesky
Banned
i use calibre PEX for my layout postsimulation, but i find a strange problem.
for sub-block A and sub-block B, when i extract the separate PEX calibreview for A and B, and simualte, the results are very bad, resolution from 10bit(presimulation) to 6bit(postsimultion) or less; while, after i make one subcircuit with A and B (for ex: called C, C contains two sub-block calibreview A and B) and simulate, the results improve a lot, resolution from 10bit(presimulation) to 8bit(postsimultion) or so; why? what is the reason?
if i want to see one sub-block's performance(for ex: A) by postsimulation, then what should i do? if i use calibreview of A and other sub-blocks with schematic in presimulation(without parasitics), then run simulation with a config testbench, is the postsimulation result reliable? or any other ways available?
besides, if i use some sub-blocks' calibreview and the other blocks' schematic view in presimulation, and run simulation for my whole circuit, then the results reliable?
finally, how to optimize the layout for better circuit performance? how to fix the main affecting wires and nets in layout?
pls help me,thanks in advance.
for sub-block A and sub-block B, when i extract the separate PEX calibreview for A and B, and simualte, the results are very bad, resolution from 10bit(presimulation) to 6bit(postsimultion) or less; while, after i make one subcircuit with A and B (for ex: called C, C contains two sub-block calibreview A and B) and simulate, the results improve a lot, resolution from 10bit(presimulation) to 8bit(postsimultion) or so; why? what is the reason?
if i want to see one sub-block's performance(for ex: A) by postsimulation, then what should i do? if i use calibreview of A and other sub-blocks with schematic in presimulation(without parasitics), then run simulation with a config testbench, is the postsimulation result reliable? or any other ways available?
besides, if i use some sub-blocks' calibreview and the other blocks' schematic view in presimulation, and run simulation for my whole circuit, then the results reliable?
finally, how to optimize the layout for better circuit performance? how to fix the main affecting wires and nets in layout?
pls help me,thanks in advance.