Strange PLL phenomenon during the transition period

[radiohead]

Strange PLL phenomenon

Hi all!

I am doing measurements on a fractional N sigma-delta PLL. Synthesized frequency: 2.5-4GHz. Reference frequency 26MHz. Channel spacing 360kHz.

Everything seems right. Using a MUXOUT pin, i get the divided RF, and REF clock with the right frequency.

But at powering up of the board, instead of a nice sinewave (with some phase noise, i know), I get a modulated carrier. It's center frequency is okay though, so the PLL does lock. When measuring on the charge pump output, I find the charge repetition frequency to be very low, like 11kHz. Much lower than what I expect from the PLL settings. And this frequency ripples through the loop filter, and produces the modulated carrier.

The ripple really comes from the charge pump, as the transitions are very steep. The opamp in the loop filter is nice and quiet and does not oscillate.

Where does this strange phenomenon come from?

Anf the queerest thing of all: after a while (eg 5 minutes), the modulation disappears, the locking is ok, and everything works as simulated with the software.

Can anybody give me a clue what is happening in the transition period? I really tried a lot, but nothing seems to work.

 

[radiohead]

Re: Strange PLL phenomenon

Forgot to mention this: it is not a temperature effect. When the PLL is locked nice, and I unpower the board and then repower it directly after that, the 11kHz is there again!

 

[divan]

Strange PLL phenomenon

How about to play with charge pump current?
will this have any effects ?
What kind of PLL IC do You use?

 

[radiohead]

Re: Strange PLL phenomenon

Charge pump current lowering has no effect. I use the ADF4153 from analog.

When the PLL is in lock, I can even set the charge pump current to the highest value for every frequency. The phase margin is 50 degrees, more than enough to deal with this extra gain.

 

[lguancho]

Re: Strange PLL phenomenon

Hi. Are you using any low drop-out voltage regulator, with proper input /output decoupling cap? Sometimes, you can get sawtooth type of ripple on the regulated LDO output if the cap is not right.

Also, are you using a signal generator as the 26MHz clock, or just some clock oscillator? Maybe it is good to characterise the clock first.

 

[radiohead]

Re: Strange PLL phenomenon

Just measured the regulator outputs once again. They're as clean as a whistle. Nothing to see here.

About the reference: I use a DDS as reference. Differential output, filtered, AC coupled into the PLL. I get a very nice sinewave here. When measured with the spectrum analyzer, no low-freq spur to be found in a 80dBc range!

 

[buta]

Strange PLL phenomenon

What is the reference for the DDS, is it a TCXO? Will the reference of the DDS take time to settle?

 

[radiohead]

Re: Strange PLL phenomenon

No, just a XO. Clear from the start. I suppose the frequency might shift a few ppm during warming up of the XO, but this cannot be the cause of my problems.

 

[E-design]

Re: Strange PLL phenomenon

I had some problems with LDO's in the past regarding noise. One of the problems is that sticking a scope probe on them sometimes quiets them down. Must say I never liked LDO's thereafter in low noise PLL applications. For me the old 723 was still king, more so after it became available in SM

 

[rfsystem]

Re: Strange PLL phenomenon

I expect that you have more than one stable operating point in your PLL. That could be because of clipping or limiting behaviour in the charge pump current versus output voltage behaviour. A normal charge pump at the middle range get reduced at the supply boundaries. If the loop filter is an active circuit the nonlinear output conductance could create a stable DC operating point with the input impedance of the active circuit. That point depend on the actual charge pump current. If a passive loop filter is used a feedback from the varactor could be the source of a similar behaviour. If some limiting parameter e.g the supply is changes also the behaviour should change. That would give some hints.

 

[xtasa]

Re: Strange PLL phenomenon

:idea:
Hi all,
I read discussion about PLL design and problem that you find. Here are some new ideas. Do you have 2.5V at the + OP input with suffition current for OP bias. I had problems with OP027 in some design similar to yours that in biasing R current have to be greater tahn 2mA. Also is important that you have OP which can go to the 0V that means that you have min -5V at -VCC ,or OP with with possibility to go down to -VCC
with only + voltage on +VCC and -VCC to the ground LM358 ..etc.IF you have not adequate OP it worked from time to time as comparator producing some low frequency avarege frequency is close to wonted but PLL IC not show that is frequency correct.
Many succes in PLL design

XTASA