strange issue with spice

Hi all,
I'm using LTspice i have to simulate a huge resistive network it looks like this

*ckt to simulate
V1 1 0 1
R2451_1 2451 1 6.464850e+003
R2471_2 2471 2 5.989400e+003
R1_3 1 3 5.501689e+003
R2483_4 2483 4 5.605715e+003
R2487_5 2487 5 6.503001e+003
...... many thousand upto maybe 200,000 lines of resistances ,
.op
.options GminSteps =0
.options SrcSteps =0
.save I(V1)
.end

i use these for fast simulation.
.options GminSteps =0
.options SrcSteps =0
may be removed and .op changed to .tran
BUT here is the interesting part!!
the current I(V1) should be negative as it is in 90% of simulation runs. ( i made small ckt again to verify if i'm making blunder ) BUT in some cases its positive, so theoretically my dead resistive network is producing current !! oops that is what is not supposed to happen :shock:
what is shocking is that atleast the sign should be same in anycase ( and negative as to my opinion) as its resistive network and only power source is V1 defined
so here i'm to ask the knowledgeable community of what is happening here. my guess was maybe tolerance is less someoverflow is happening etc.
can you help me
i've not changed any other default value.
I'm stuck and stumbled by what is happening.
any ideas and help is greatly appreciated and maybe its a good lesson for me to be aware of simulation results

To find a solution for each time-step, the simulator algorithm goes through a number of iterations.

With each iteration it gets closer to the answer, until it converges on consistent figures for V, A, W, R, etc., in all components. Then it sends the results.

That's the idea anyway.

The more complicated the circuit, the greater the number of iterations that are required, and the longer it takes to generate each frame.

200,000 components is a lot for a simulator to handle. I would not be surprised if the simulator says 'okay, I did 100 iterations, that has to be enough, even if the answer is off. Gotta move on.'

A programmer wants his simulator to give a good performance, when users compare it to other simulators.

Did you test the results with fewer resistors? Say, 1,000? Did you get proper results then?

thanks for the reply,
Yes i did checked with fewer components in fewer components its fine. In case of LTspice i found that changing solver to alternate solves the problem. BUT now i'm not sure if the artifacts of simulation will affect the result in some other wasy. one another thing i tried was making voltage source bigger so that at no node current drops to low value.
My guess was that some where in internal nodes the current in some of branches is getting neglected because it was too small (numerically) so what was happening was extra current in opposite direction was added so to sum to proper value. this summed up resulted in a total current which was needed in counter intuitive direction just to have KCL happy!
for now trouble is gone, thanks for the idea, I lack the documentation about many control parameters. Maybe a longer explanation about how they could affect the simulations would make simulation more better at least to a newbie like me

vijaydeepbhatt said:

one another thing i tried was making voltage source bigger so that at no node current drops to low value.
My guess was that some where in internal nodes the current in some of branches is getting neglected because it was too small (numerically) so what was happening was extra current in opposite direction was added so to sum to proper value. this summed up resulted in a total current which was needed in counter intuitive direction just to have KCL happy!

Click to expand...

Yes, this is what we have to do with simulators. Each has its limitations and each is capable of generating misleading results.

It helps if we know how the algorithm calculates results. Then we'll know what things to try in order to get the best performance from it.

Naturally it also helps that you (a) had some idea of what the correct outcome should look like, and (b) you examined closely enough to realize that things were 'off'.

- - - Updated - - -

vijaydeepbhatt said:

one another thing i tried was making voltage source bigger so that at no node current drops to low value.
My guess was that some where in internal nodes the current in some of branches is getting neglected because it was too small (numerically) so what was happening was extra current in opposite direction was added so to sum to proper value. this summed up resulted in a total current which was needed in counter intuitive direction just to have KCL happy!

Click to expand...

Yes, this is what we have to do with simulators. Each has its limitations and each is capable of generating misleading results.

It helps if we know how the algorithm calculates results. Then we'll know what things to try in order to get the best performance from it.

Naturally it also helps that you (a) had some idea of what the correct outcome should look like, and (b) you examined closely enough to realize that things were 'off'.