shaiko
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Hello,
Using Active HDL - I've been simulating a synchronous FIFO created by Altera's IP Catalog.
This is the instantiation of the FIFO:
I simulated the design by applying stimuli to clock , wrreq and rdreq.
When wrreq = '1' - "usedw" and "empty" get updated on the rising egdge as expected. However, the actual content of the FIFO's memory matrix gets updated only on the falling edge of the clock...
Why is that?
Please review the attached waveform.
Using Active HDL - I've been simulating a synchronous FIFO created by Altera's IP Catalog.
This is the instantiation of the FIFO:
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altera_fifo IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END altera_fifo;
ARCHITECTURE SYN OF altera_fifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
q <= sub_wire2(7 DOWNTO 0);
usedw <= sub_wire3(3 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "ON",
intended_device_family => "Stratix V",
lpm_numwords => 16,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 8,
lpm_widthu => 4,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2,
usedw => sub_wire3
);
END SYN;I simulated the design by applying stimuli to clock , wrreq and rdreq.
When wrreq = '1' - "usedw" and "empty" get updated on the rising egdge as expected. However, the actual content of the FIFO's memory matrix gets updated only on the falling edge of the clock...
Why is that?
Please review the attached waveform.