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strange behavior of ADC Module

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garimella

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I am using a breakout board of AD7606 module. I have been using for a while without any problems. Off late I had developed a interface board to FPGA. This interface board houses ADC and translates 5V to 3.3V to FPGA. I am generating convert pulses from FPGA and mysteriously ADC module does not generate Busy pulse although FRST output pin from ADC shows up. I have changed almost 3 ADC modules and I end up in the same problem. I could not figure out the reason behind this behavior.
 
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Strange, If I assert Reset repeatedly, busy pulse appears. As per data sheet Reset is asserted only once
 
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I followed exactly as per POST #2 in parallel mode configuration. My problem is that Busy Bit appears only after repeated assertions of RST pin.
 
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You refuse to provide usueful informations...

With this .. you don´t hurt us, you hurt yourself.

Klaus
 
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I am unable to share schematic without customer's consent. However, I made few experiments. There is no problem with the PCB and all the outputs from FPGA are properly generated and reach the input pins of the ADC. ADC has been properly configured for the range, IO Drive and for parallel read operations.
I have followed the scheme of timing as shown below
ADC_Timing.png


List of observations

1. At first I generate CONVSTA,CONVSTB signals (as per datasheet)--> Result, I get the Busy Pulse(4us) perfectly
2. I generate Chip select (CS_Bar) along with convert pulses--> Result, Again I get the Busy Pulse(4us) perfectly
3. Now I generate RD pulse along with the above signals--> Result, Busy Pulse disappears.

When I remove RD pulse, Busy pulse re-appears. I am using break outboard from ali express and it had worked earlier with arduino. I have changed 3 modules, removed from a working system and I get the same response. What could be the problem?
 
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You are observing this :

Reset Input. When set to logic high, the rising edge of RESET resets the AD7606/AD7606-6/AD7606-4. The device should receive a RESET pulse directly after power-up. The RESET high pulse should typically be 50 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied during a read, the contents of the output registers reset to all zeros
Click to expand...

Regards, Dana.
 
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Unfortunately my scope does not have a recording feature. I am applying reset for a duration of 1 us , just after the power up and all activity begins post reset.
 
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Using your DSO to detect runts, no hits on any control pin ? Pulse width trigger no foreshortened Pulse
width on any pin.

Supply pins clean, DSO on infinite persistence, AC, edge triggered, 50 mV, turn G up, whats
pk-pk rail noise ?

DSO on fast frame, no random glitches observed on any pin..... ?


Regards, Dana.
 
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Hi,

Basic question:

* why do you refuse to show your signals on a scope?

Klaus

Maybe Dana is on the right track:
Maybe you just left the RST input floating and it picks up the signal form your RD pulse nearby. (We can not see this...)

You don´t give use the chance to help you. You don´t give photos, no schematic, nothing we can validate.
How often do we see in the the forum "I did everything as the datasheet says" ... but when we see the true story, we detect here a mistake, there a missing signal, there not keeping on standard rules...
And after we explained the reason we can read: Oh, I didn´t know this or that was important ....

And that´s exactly the probem with a textual description. You only tell us what YOU think is important ... and don´t tell the whole story.
A picture shows everything. what you think is important, but also what you think is not important. And it needs no translation.

Klaus
 
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