Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Strained S/D mask layout rule DRC

Status
Not open for further replies.
M

mark85

Newbie
Newbie level 4
Joined
Jan 18, 2023
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
27
What this SSD.DN.1 DRC error mean? What causes it? How to avoid or fix it?
 

Sort by date Sort by votes
Dominik Przyborowski said:
Read message carefully or open design rules manual and search for this rule.
Click to expand...
Ya,
I searched DRM but diagram is not given for the same, what I deduced from what is given in DRM is attached with this message.

Am I correct about this?

Screenshot 2023-02-24 193445.png
 

Upvote 0 Downvote
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top