smartind
Newbie
stop line wrapping in Design Compiler "write_file -format verilog ....." command
I'm getting line wrapping in the verilog file output from Design Compiler.
Which is causing problems later in the design flow.
This seems like it would be easy to fix in Design Compiler, but I don't
see any control switches for the "write_file" command, when I do
"man write_file" in DC.
So I searched the 2014 DC User Guide, and did not find anything about
controlling line wrapping. And a Google search did not find anything.
Is there an "attribute" that I can set inside DC that controls
line-wrapping on hdl writes ? Note, I can fix this with a perl script,
but prefer to fix this at the source.
thanks,
-steve
I'm getting line wrapping in the verilog file output from Design Compiler.
Which is causing problems later in the design flow.
This seems like it would be easy to fix in Design Compiler, but I don't
see any control switches for the "write_file" command, when I do
"man write_file" in DC.
So I searched the 2014 DC User Guide, and did not find anything about
controlling line wrapping. And a Google search did not find anything.
Is there an "attribute" that I can set inside DC that controls
line-wrapping on hdl writes ? Note, I can fix this with a perl script,
but prefer to fix this at the source.
thanks,
-steve