Step response questions, stability problem, compensation

[kidmanbasha]

step response

1- When a step signal is applied to a common source ( or any circuit with a feed forward path) at the time the input pulse is rising, the output of the common source is also rising in the same direction and not the opposite although the gain of the CS amp is -ve. This happens because at that moment the o/p seen is only due to the feed forward path and not the amplifier because the transistor hasn't still started to respond to the pulse. The question is, how come if the step input's amplitude is VDD, the peaking that happens at the o/p of the CS amp at the beginning exceeds the amplitude of the input pulse? Shouldn't it be less due to a capacitive divider?

2- In EE240 2009 Advanced Analog Design Elad Alon doesn't approach the stability problem from a frequency response stand point i.e. phase margin and gain margin issues. Instead he looks and the step response which I think is more realistic. So I wanna know if people to approach stability issues from a time domain stand point ONLY or not.

3- How can compensation be made when looking at stability in time domain?

 

[FvM]

stability step response

2. In various applications, system behaviour in time domain is the primary quality criterion, e.g. with pulse amplifiers or control theory. It's of course related to small signal frequency domain representation but also involving large signal effects.
3. As far as I know, mainly empirical parameter optimization according to a defined quality criterion is applied in time domain, in some cases also simplified tuning methods, e.g. ziegler-nichols for PID controllers.