[SOLVED] std_logic values in vhdl

[pulkit.vlsi]

there are 9 values in STD_LOGIC, in VHDL.

0,1,X,Z,U,W,H,L,-

What is there significance in terms of hardware.

 

[yadavvlsi]

Check this:
https://www.edaboard.com/threads/123766/

 

[xtcx]

What is there significance in terms of hardware.

What do you mean?. Asking what in hardware will 'x' generate?.
Into hardware '0'\'1'\'Z' is all that matters. All others are ignored.

 

[yadavvlsi]

When chip is powered up. State of all memory elements will be unknown i.e X

 

[TrickyDicky]

Actually, 'U' would be more appropriate at powerup, for uninitialised. But this all goes back to the origional intention of the language - it was meant for simulation of analogue logic circuits. Hence all the extra values. Synthesis came along way after the language. On real hardware, if a memory hasnt been initialised, you'll actually find its all '1's and '0's. On FPGAs the only appropriate values are '1' and '0', with 'Z' for tristate outputs only. 'L', 'H', and other values can be used in code, and will be synthesised accordingly into the most appropriate logic, but on the actually hardware, all yoou get is '0' and '1', hence possible simulation synthesis missmatches.

 

[FvM]

Although not used in synthesizable hardware descriptions, 'L' and 'H' can be seen as a representation of hardware features like weak pull-up or pull-down resistors and input hold circuits.

 

[xtcx]

When chip is powered up. State of all memory elements will be unknown i.e X

Well, 'unknown' 'x' cannot be described in FPGAs . Maybe while powering up ( ie when the core voltage steps up from zero to it's operating range) it is called unknown but after power-up completes, all it can have is either 0 or 1. It can be uninitialized or initialized. No other levels of voltage can be used to define logic. However in simulation you can have 9 possible states for std_logic.

I dont know in case of ASIC\SOCs designs

 

[pulkit.vlsi]

Thanks everyone for the reply....