Static Timing: Usage level sensitive latch as driver of clock-domain-crossing path. Why not ?

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shaharkl

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Hi,
Among the most common async clocks data interface designs is the gray pointer FIFO designs.
Commonly the FIFO is an array of sequential cells at the transmit side.
Also common is to implement this array using edge triggered DFF (unless your design is latch based...).
Why not use level sensitive latch cells to implement this array ?
I am looking for answers both from static-timing-analysis point of view and also from CDC design perspective .
Thanks
SK
 

I believe STA depends on clock events and a latch will also propagate "data events" outside that heartbeat and muss up its mind - leading to design style rules to accommodate its brittle nature?

In my interactions with "digital guys" it seemed to me that it was about getting the tool to be happy, without regard or exception to whether the circuit works.

And nobody wants to rouse the Methodology Harpies from their nap.
 

Could be testability reasons. DFF-based design is always preferred over latches -- maybe that crossed over to CDC analysis.
 

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