Static Timing Analysis ...........setup time calculations with 40 percent duty cycle

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sajju32

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Hi guys a similar question was asked in recent test , can anyone please tell me how solve this question "A timing analysis shows that an ASIC has a clock skew of +/- 250ps. The flip flops used have a clock->Q delay of 120ps, an input setup time of 80ps, an input hold time of 375ps. The duty cycle of the clock is 40%. The operating voltage of the ASIC is 1.8V. If the ASIC is to run at 490MHz how much logic delay can be in the path? "

Thanks
Sathish
 

mail4idle2 said:
1590 can be logic delay.
2040 - (120+250+80) = 1590 ps
Click to expand...

Hi mail4idle2, thanks for your answer. I have doubt here, what about the 40 percent duty cycle? Do duty cycle don't have any impact on calculating logic delay
 

For one cycle max path (setup requirement) we do not need the 40% duty cycle
If it half cycle path then we would need it.
 
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