static timing analysis & its modes

[veenashree89]

hi all.....

I am new to STA...i just want to know.,wat are are the modes need to be cleared in sta..and at which stage of ASIC design we perform different modes of STA..please suggest some links to know more about this...

 

[yadavvlsi]

There can be n number of modes present in a design. e.g functional mode, scan mode, MBIST mode etc.
https://www.ee.bgu.ac.il/~digivlsi/slides/STA_9_1.pdf
https://docs.google.com/viewer?a=v&...00ODRjLWFmN2EtOTIxYzAwMTNkZjNi&hl=en_US&pli=1

 

[jeet_asic]

Input to an STA tool (primetime) is a netlist (Verilog , VHDL ,EDIF) , delay formats , library formats . STA is performed at pre-layout n again at post-layout stages. It is performed to check whether your design meets setup n hold specifications or not n other spec. like input delay , transition , output delay as per your design specifications. and lot of other things.

Get more info here "Timing Paths" : Static Timing Analysis (STA) basic (Part 1) |VLSI Concepts

 

[veenashree89]

ok..how to specify Sta modes,and where?

 

[raju3295]

sta modes are nothing but the way you apply the constraints, depending upon the mode, generally variation in the case analysis of the ports will create the modes

 

[veenashree89]

ok..can i know,how we specify it in prime time..