Static power analysis vs Dynamic power analysis .

[LaxmiNarayanan]

Could you please explain static power analysis ? Dynamic power analysis ?
And , why is it preferred over dynamic power analysis ?
W.R.T. clock tree synthesis .

 

[vijayR15]

Hai narayanan,

Static power analysis is analysing the power when there is no change in input..

Dynamic power analysis is analysing the power when the input changes its state often.. Dynamic power dissipation invovles charging and discharging of capacitances.

In clock tree synthesis, switching of input will happen thats why we are calculating this dynamic power.. so that we can calculate the maximum level..

i use report_power to calculate the value in encounter..

Refer below to get more

 

[jeet_asic]

Are their any specifications on what type of clock must be used . I mean to say that , clock with sharp edges use more power. {I read this somewhere}.

Correct me if i am wrong.

 

[vijayR15]

Hai jeet_asic

Types of clock will be based on RTL coder..(ex:- synchronous clock, asyn etc..,)


Also clock with rapid pulse variation[up and down] will consume more power.. I think u said the same.....