"State Machine" in LTspiceXVI

[pancho_hideboo]

"State Machine" in LTspiceXVII

Following netlist is an example of "State Machine" from LTspiceXVII Help.

* divide by 2 example
V1 1 0 pulse(0 1 0 1u 1u .5m 1m)
V2 c 0 pulse(0 1 0 1u 1u 5m 10m)
R1 2 0 1K
R2 3 0 1K
R3 4 0 1K

.machine
.state S0a 0
.state S0b 0
.state S1a 1
.state S1b 1

.rule S0a S0b V(1) < .5
.rule S0b S1a V(1) > .5
.rule S1a S1b V(1) < .5
.rule S1b S0a V(1) > .5
.rule * S0a V(c) > .5

.output (2) V(1) < .5
.output (3) V(1) > .5
.output (4) state
.endmachine

.tran 30m
.end

What does this "state" mean ?

 

[pancho_hideboo]

This ".machine ~ .endmachine" describes a sequential block which has four states, two inputs and three outputs.

BTW, state transition diagram in the following does not match to netlist description.
https://www.analog.com/media/en/tec...rnal-v1n1-2018-03-di-ltspice-gabinoalonso.pdf