[SOLVED] 'state is unconnected in block' verilog code error

module pulse_generator(clk,reset,s,x,P,L);
input clk,reset,s,x;
output reg P,L;
localparam s0=00,
			 s1=01,
			 s2=10,
			 s3=11;
reg [1:0]state;
reg [1:0]next_state;
initial state<=s0;
always@(negedge clk)
begin
	state<=next_state;
end
always@(negedge clk or posedge reset)
 begin
	if(reset)
	 next_state<=s0;
	else
	begin
	 case(state)
	  s0: begin
				if(s==1)
					next_state<=s1;
				else if(s==0)
					next_state<=s0;
			end
	  s1: begin
			if(s==1)
				next_state<=s2;
			else if(s==0)
				next_state<=s0;
			end
	  s2: begin
			if((s==1)&&(x==0))
				next_state<=s3;
			else if((s==1)&&(x==1))
				next_state<=s1;
			else if(s==0)
				next_state<=s0;
			end
	  s3: begin
			if((s==1)&&(x==1))
				next_state<=s1;
			else if((s==1)&&(x==0))
				next_state<=s3;
	      else if(s==0)
				next_state<=s0;
			end
	 endcase
 end
 end
always@(state)
begin
	case(state)
	 s0:begin
			P=0;
			L=0;
		 end
	 s1:begin
			P=1;
			L=1;
		 end
	 s2:begin
			P=0;
			L=1;
		 end
	 s3:begin
			P=0;
			L=1;
		 end
	endcase
end
endmodule