It is my mistake, I think vicky's suggest is right.
When the gate of P1 connects vss, the function looks right.
The "logic 1" is not real power supply voltage, when vdd increase
but under 1V, P1 will output the VDD value, the value is under 1V, but this
voltage need to driver N2 to turn on, so the size of NMOS I think can't the
same when you want a start up function.