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For maximum efficiency always use the largest possible grid size, this will depend on the components used and board density.
For older style analogue using SOIC devices I will use a grid of 0.635mm if the board isn't that dense... for HDI analogue designs using full metric footprints to IPC-7351 standard I will use a grid of between 0.25 - 0.05mm depending on the density of the area I am working in.
A larger grid minimises the amount of Cartesian points you can snap too, so the larger the grid the more efficient your layout will be and tidier. You also have to think about trace widths and trace to trace spacing but planning this all out will pay dividends. Those of us who started of doing hand tape ups learnt this instinctively as we did tape ups, those who started on CAD tend to be sillier and use very small grids, these are inefficient and lead to too many data points.
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