Standard deviation for effective channel length? (45nm)

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dnanar

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Hi,


I'm trying to find a reference for computing or getting a (not so) gross value for the standard deviation for effective channel length (to perform a monte carlo analysis on my circuit). Despite looking for, I couldn't find anything except it probably follows a law of the type A/sqrt(M*W*L) with A a constant depending of the process and M a moderation factor. My transistor fabrication process is a standard 45nm process.

It's quite surprising I couldn't find anything about Leff. I'm studying the variation of Leff and Vth, and I could find things on Vth (such as: https://www.edaboard.com/threads/211503/ or more recent https://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5755188), but nothing on Leff. Any help is greatly appreciated.

Thank you!
 
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