standard cell verifcation

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research235

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Hello all

I have some 800 standard/library cells . I want to do the physical verifation(DRC/LVS) using calibre. Is it possible to check for all the cells at one run .
I have all the cells as a signe gds2 file .. and a single cdl file with no single top level cell .. can soem one help me with is ..


thank you

Suresh
 

Hi,
It was long time ago, when I did it last time. May be I will give it a try.
Make a verilog file.
Instantiate all cells in it, short each input of each cell except the clock pin and make this net as an Input Port.
Short all clock pins of each cells, make it another input port
Then make a bus of all output ports.

This is your top level.
Read it in your floorplan tool to get a cdl, and pnr it to get a layout.
then run DRC/LVS
kr,
Avi
http://www.vlsiip.com
 
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