standard cell problem

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r94

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hii..
what will be the effect of reducing height of standard cell on timing and area of chip??
 

Smaller area, slower timing, unless you reduce it too far, of course.
 

thanks for reply...but i still have a doubt...
if we reduce the height ,should'nt the area should increase for a particular chip so that volume remains constant.
and can you elaborate more on how the timing wll be slower??
thanks in advance
 

r94 said:
hii..
what will be the effect of reducing height of standard cell on timing and area of chip??
Click to expand...

Eg: height = 20um
Width of nMOS and pMOS = 7um each for a simple inverter
Width is less, Current is less hence delay is more
Area is less as width is less .
Density Design

Eg: height = 30um
Width of nMOS and pMOS = 12um each for a simple inverter
Width is more, CUrrent is more hence delay is less
Area is more as width is more.
Performance design.

Conclusion : You are reducing the width of mos with less cell height.

Hope this helps .

Regards,
PAM
 
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