Standard cell design topic

Hello guys,
I am designing standard cells and I believe that advice from standard cell designer expert will indeed helps me a lot. I have several doubts about define standard cell:

1. How can we define the input slew rates and output load capacitance for characterizing standard cell?
2. How do people define logic gate with drive strength 1X? The logic gate with minimum width and length will have a drive strength 1X, is it correct? Then, How to derive the drive strength 2X from 1X specification?

Thank you so much and looking forward your help.

input slew is defined. Use the fastest inverter in your design without any load. Find out the output transistion times(rise/fall). that will be the fasted transition time you will get. On a higher side find out from your Physical design team as to how much is max transition time they want to allow ( this is done using coupling simulations). then divide the difference by 7 and generate the points.( 7 is usually the number of slew points recommended by the Liberty file and the tools that use it.
Load is fanout of 1X,2X,4X,8X,16X,64X for each strength of the gate.
1X is defined as the single finger inverter in standard cell height. it is not the minimum, you can always have sub-finger devices to reduce leakage when the sub-finger inverter is used for non-timing critical paths.

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input slew is defined. Use the fastest inverter in your design without any load. Find out the output transistion times(rise/fall). that will be the fasted transition time you will get. On a higher side find out from your Physical design team as to how much is max transition time they want to allow ( this is done using coupling simulations). then divide the difference by 7 and generate the points.( 7 is usually the number of slew points recommended by the Liberty file and the tools that use it.
Load is fanout of 1X,2X,4X,8X,16X,64X for each strength of the gate.
1X is defined as the single finger inverter in standard cell height. it is not the minimum, you can always have sub-finger devices to reduce leakage when the sub-finger inverter is used for non-timing critical paths.

- - - Updated - - -

input slew is defined. Use the fastest inverter in your design without any load. Find out the output transistion times(rise/fall). that will be the fasted transition time you will get. On a higher side find out from your Physical design team as to how much is max transition time they want to allow ( this is done using coupling simulations). then divide the difference by 7 and generate the points.( 7 is usually the number of slew points recommended by the Liberty file and the tools that use it.
Load is fanout of 1X,2X,4X,8X,16X,64X for each strength of the gate.
1X is defined as the single finger inverter in standard cell height. it is not the minimum, you can always have sub-finger devices to reduce leakage when the sub-finger inverter is used for non-timing critical paths.

Thank artmalik,

But I still don't understand how to define the specification for the gate of 1X, 2X, 4X.... drive strength. For example with gate INV_X1 and INV_X2, what should be the W/L for them assuming with 65nm node?

Thank you so much.

1X means single finger device driving itself. You have to measure the pin_cap for inverter and that is the cap which you need. 2X means load of two inverters connected togther(inputs connected together) and so on.
Length will be 65nm or more depending on the library. Width is determined by Wpmos+Wnmos=Total height of the cell. The standard cells are based on certain height which is determined by the routing resources, no of tracks, flip flop layout. usually 9 tracks or 12 tracks of routing. Wpmos and Wnmos are swept across different values to get a equal delay for rise and fall.