stable sigma-delta modulator

sigma delta modulator stable

Hi all,
What does it mean - the sigma-delta modulator is stable.
And how it can be check?

Thanks.

stable sigma delta

sigma-delta modulator (SDM) is analog block with negative feedback. It can incorporate one and more integrators in loop, so it can lead to unstability for orders, higher than 2.
Architectoral choice is important for high order SDM. Better to educate issue with special papers,- there are a lot of possibilities to built a high order stable SDM.

sigma delta stability

mikersia said:

sigma-delta modulator (SDM) is analog block with negative feedback. It can incorporate one and more integrators in loop, so it can lead to unstability for orders, higher than 2.
Architectoral choice is important for high order SDM. Better to educate issue with special papers,- there are a lot of possibilities to built a high order stable SDM.

Click to expand...

Hi mikersia,
But how can I check (with simulation) the modulator is stable or not?

Thanks.

sigma delta modulator site:edaboard.com

There are unconditionally stable architectures, e.g. Mash,
where high order structures are implemented basing on first-second orders SDM. Then you can take most suitable structure from a huge number of described in literature, and
of course, you can to do behavioral simulations with MathLab for own structure. In Cadence environment it is possible to use Verilog-A to write a behavioral model. Behavioral model can be written even in standard Verilog for DC signal.

Added after 11 minutes:

Analog simulation is also possible for not complex structures. But it is better to simplify overall schematic, replacing of a real schematic of OAs, comparators, logic components by it's simplified models, e.g. as shown in figure


Added after 2 minutes:

https://obrazki.elektroda.pl/87_1242205769.jpg

stable sigma delta

mikersia said:

There are unconditionally stable architectures, e.g. Mash,
where high order structures are implemented basing on first-second orders SDM. Then you can take most suitable structure from a huge number of described in literature, and
of course, you can to do behavioral simulations with MathLab for own structure. In Cadence environment it is possible to use Verilog-A to write a behavioral model. Behavioral model can be written even in standard Verilog for DC signal.

Added after 11 minutes:

Analog simulation is also possible for not complex structures. But it is better to simplify overall schematic, replacing of a real schematic of OAs, comparators, logic components by it's simplified models, e.g. as shown in figure


Added after 2 minutes:

https://obrazki.elektroda.pl/87_1242205769.jpg

Click to expand...

mikersia, but how can I check with simulation is it stable or not ????
I need to probe some voltages may be...........or ...........I do not know.

mikersia

Stability analisis of SDMs - is lovely themes of a lot of dissertations. A simplified analysis can use discrete time (z-domain) small signal transfer function to have system frequency responce. But a nonliner quantizer in feedback loop creates signal dependent stability problem. So from side of analytical investigation is better to read special literature, starting from authors J.C. Candy and R.M. Gray. See attached papers also.
To investigate one concrete implementation is better to use behavioral or Spice simulations even for DC input signal. In that case observation of output integrator voltage will give answer. First criteria is absence of voltage saturation during a few cycles,- feedback should force intgrator's voltage to swap around common mode level.