Stable CE to unstable CE ?

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JPdP

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I would like to use the CE topology for an DRO Oscillator design but, I just doen't get the topology unstable. I've tried an inductor and later an capacitor in shunt with a resistor at the emitter to ground, to see if I can get K < 1 , |S11| and |S22| >1. I just can't get it to work.

Any tips/ideas would greatly be apresiated.

regards
 

Well, that is pretty unusual. I usually have all sorts of trouble making anything stable!!! What are you using, fet, bipolar, frequency? Maybe you need a device with more gain at your frequency. Just about any common base transistor will easily go unstable.
 

I've tried the AT41470, AT41486 and BFP420 transistors @ 4.7GHz. In common base they are unstable, but I need to know if it is possible to make these transistors unstable in Common Emitter configuration.

I'm busy researching DRO's using BJT's and would like to learn these techniques/tricks.

regards
 

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