Stabilizing voltage comparator output for binary logic.

[Veaya]

Hi everyone, I'm currently designing a flash ADC in 200 nm tsmc. In the attached screenshot we're comparing a differential voltage from 599 - 600 - 601 mV @ 1 GHz. I remember in one of Razavi's papers that he used a SR latch to stabilize the output between either a high or low voltage. Unfortunately, I am unable to do the same due to the inverted nature of my output, and when I tried a simple inverter, it just completely messes up the output, probably due to parasitic capacitances and whatnot. I'm wondering if anyone has recommendations on a circuit to stabilize the output, and so that the comparator output isn't affected (too much) by what we attach to the output. Thank you!

 

[BradtheRad]

due to the inverted nature of my output... and so that the comparator output isn't affected (too much) by what we attach to the output.

SR latch can be configured using 2 NPN or 2 PNP (or 2 NAND gates or 2 NOR gates). It depends on what quiescent state you wish, and whether it acts on one polarity of logic or inverted logic.

A buffer stage or current mirror might do the job you need at the output of your project.

 

[KlausST]

I'm wondering if anyone has recommendations on a circuit to...

we don´t see your current circuit ... thus it´s hard to give recommendation on improvements of your circuit.

Klaus

 

[Veaya]

we don´t see your current circuit ... thus it´s hard to give recommendation on improvements of your circuit.

Klaus

Klaus, here's the attached schematic below.

SR latch can be configured using 2 NPN or 2 PNP (or 2 NAND gates or 2 NOR gates). It depends on what quiescent state you wish, and whether it acts on one polarity of logic or inverted logic.

A buffer stage or current mirror might do the job you need at the output of your project.

How would I go about implementing these, or can you point me to some resources where I can view how they're implemented or other designs.

Thanks.

 

[BradtheRad]

can you point me to some resources where I can view how they're implemented or other designs.

Simple tutorial illustrating SR flip-flops in two topologies (NAND gates, NOR gates). Truth tables are opposites of one another. It has to be reworked to go with components in your circuit.

build-electronic-circuits.com/s-r-latch/

 

[Veaya]

Simple tutorial illustrating SR flip-flops in two topologies (NAND gates, NOR gates). Truth tables are opposites of one another. It has to be reworked to go with components in your circuit.

build-electronic-circuits.com/s-r-latch/

Ah yes, the set reset latch will be easy to implement - I will be using the NOR version, but I was most primarily interested in the buffer stage/current mirror, because I can't use latches and progress if I don't have circuitry that stops the output being ruined if I attach a latch to it.

 

[BradtheRad]

This is a guess. It sounds as though your next stage loads the output. Often other members post schematics consisting of various mosfet arrays. And often the supply voltage is only 1 or 2 volts. I'm not sure your mosfets conduct enough current so they can drive much load (whether to source or sink current). Some kind of buffer is usually called for. In other words high input impedance, low output impedance. I'm unfamiliar with circuitry that runs at 1 GHz so my suggestion can only be vague.

 

[dick_freebird]

Be a little more clear about what you mean by "stabilize".

Clocked comparators tend to have a latching nature,
the cross-coupled gated load will "snap in" to whatever
the state is that it "hits into". This latch may, or not,
reject subsequent input difference changes while clock
remains active, depending on the hysteresis baked in
(regenerative loads can be linear below 1:1, hysteretic
above).

A lag-clock could snatch the latched difference before
it has time to wander. I'd take signal off the NMOS
clocked loads to drive NMOS common source switches
against a pair of passive loads to get full scale logic
swing, apply those to a JK latch with lag-clock, tune
it right and you've got data that will persist until next
sample.

 

[KlausST]

To me this looks like "IC design" --> thus you should have posted in the IC design section of edaboard.

as already written: please describe what you mean with "stabilize".
* my ideas: add a hysteresis to stabilize the output against noise.
* use a latched / clocked output .. to be able to freeze the output as you like

Klaus