Stability Analysis for Bandgap

[KGF KING]

Hi All,

I'm trying to simulate stability analysis in cadence using iprobe. Do anyone know that with current cadence version do we need to at VDC with dc volt =0 and acm =1 at the negative input of the bandgap opamp? Is there any cadence manual to refer and if yes where to get it? Btw the i break the loop and place the iprobe between the output of opamp and gate of my pmos which supply current to CTAT and PTAT branch.

 

[sidun.av]

Hi,

You don't need any AC sources in your schematic if you are using stb analysis. The probe injects the test signal directly into the loop. Inserting an iprobe between the output of the opamp and the gate of PMOS is correct because you are breaking both loops.
For STB analysis you can use the following tutorial:

Hopefully, that helps.