[STA] SetUp/Hold Violation fix scenarious

Hello All,

There are 3 basic paths where the SetUp/Hold violations may occur:
- inputs-to-register path
- register-to-outputs path
- register-to-register path

What are the ways to fix them on each one of the paths. Will the methodology be different depending on the path where it's used?

Thank you!

I dont think setup/hold violation can occur on register to output. But others can correct me.

First, are you getting any of these failures? If yes, show us the log file and the design.

"I dont think setup/hold violation can occur on register to output" - I still think that they may occur there - all depends on the output delay constraints.

oki .. actual ans -- of how we can fix these path will be very large. But in simple words there are different ways or u can say that there are different priorities of fixing .. but at the end the no of ways are same.

There are 3 basic paths where the SetUp/Hold violations may occur:
- inputs-to-register path -- actually if there is any violation in this path then first you have to see the "set_input_delay" setting. By changing the value you can fix this path.
- register-to-outputs path -- same with this case.. you can do concentrate on set_output_delay setting.

So basically these 2 can be managed by timing budgetting of a particular block. if you want to fix these inside the block, you can also use buffer/delay inside the block, else add these delay and all outside the block. ANd for the block the effective value of the delay changes and that can be fixed by setting different value of set_input_delay/set_out_put delay.

- register-to-register path .. all the general ways like delay insertion/swapping/resizing ..etc will be the part for this path in case there is any violation.

I hope you get my point.

So bottome line - no different ways to fix the issues only the difference is the priority/sequence (recommended) for applying different technique for fixing the violation.

What do you mean under "swapping"?

How swapping the cells may fix the timing?

hi Dmitrl,

Swapping between HVT and LVT cell.

ok, now it's understood, thank you

Register to Register path

Setup can be fixed by
1.Upsizing combinational cells that are nearer to capture flop
2.using LVT cells
3.Inserting buffers
Hold can be fixed by
1.Downsizing combinational cells that are nearer to capture flop
2.Using HVT cells
3. Inserting delay buffers

In Input to Register path
setup and hold can be fixed by constraining input delay and clock period

In register to output path
setup and hold can be fixed by constraining output delay and clock period

In input to output path
setup and hold can be fixed by min and max delays

Thanks & Regards
D.Raviteja

insertion buffers for setup fixes - did you mean CTS buffers on clock tree?

No we insert a strengthen buffer near to the input pin of capture flop

No we insert a strengthen buffer near to the input pin of capture flop

Click to expand...

Could you explain why you put the buffer CLOSE to the capture flop and not in the middle of the line/wire/route? Should this way the slop be fixed better?

Because there may be other paths passing through or originating from the flop nearer to lauch flop. Hence buffer insertion may affect other paths also. It may improve all those paths or degrade. If all those paths have violation then you may insert buffer nearer to launch flop provided it improves slack.

ravipandu46338@gmail.com said:

No we insert a strengthen buffer near to the input pin of capture flop

Click to expand...

By considering which timing (setup or hold) fix, you said the above statement.

If it is for setup, if you insert near to capture flop, it doesn't work. For better results, we should insert at the center of the wire.
In PT shell, you can't see better results if you use "insert_buffer" command.
We should go to PD team & have to tell them to insert manually at the center of the wire. Then only it will work.
If you provide ECO file for them, tool will insert some where else. Then, we may not see good results.

regards,
Subhash C

By considering setup fix,i said it...,you just go through the below answer

(buffers are inserted for fixing fanout voilations and hence they reduce setup voilation; otherwise we try to fix setup voilation with the sizing of cells; now just assume that you must insert buffer !)
Near to capture path.
Because there may be other paths passing through or originating from the flop nearer to lauch flop. Hence buffer insertion may affect other paths also. It may improve all those paths or degarde. If all those paths have voilation then you may insert buffer nearer to launch flop provided it improves slack.

if you insert buffer in the middle how we can fix setup time violation even though this path may be fixed but the other paths orginating from the launch flop will be violated