STA Problem with Encounter

[Fahmy]

Hi All,
I am encountering an STA problem with SoC Encounter.

In the design I am working on, there are some registers with both set and reset driven by some logic . This logic can be triggered by a clock. This logic is designed in a way that assures that only one of them (either set or reset) could be active at a time. However Encounter doesn't recognize the logic relationship between the two signals and reports a violation due to the simultaneous deassertion of both set and reset (driven by the same clock edge) which I am sure that this violation isn't true.

My question is that is there a way by which I can instruct the tool to discard this type of violations ? Or to consider the logical function when doing STA ? (without disabling any other timing check that could be real)

Best Regards
Fahmy

 

[shelby]

this will disable the asynchronous check on a per flop basis. i forget the exact syntax but its something like this ...

set_disable_timing -from SET -to RESET [get_lib_cell FLOP*]
set_disable_timing -from RESET -to SET [get_lib_cell FLOP*]

 

[Fahmy]

Hi Shelby
Thanks for your help. but unfortunately it didn't work because the the tool doesn't see a path from set to reset. It sees to paths that are racing together one from the clock driving the combinational logic to the set and the other is from the same clock to the reset .

Setting false path on one of these two paths could hide another real timing checks ..


Do you have another idea?

 

[shitansh]

You need to disable set and reset one by one to perform proper recovery and removal check.

HTH
Shitansh

 

[entropy]

Hi All,
I am encountering an STA problem with SoC Encounter.

In the design I am working on, there are some registers with both set and reset driven by some logic . This logic can be triggered by a clock. This logic is designed in a way that assures that only one of them (either set or reset) could be active at a time. However Encounter doesn't recognize the logic relationship between the two signals and reports a violation due to the simultaneous deassertion of both set and reset (driven by the same clock edge) which I am sure that this violation isn't true.

My question is that is there a way by which I can instruct the tool to discard this type of violations ? Or to consider the logical function when doing STA ? (without disabling any other timing check that could be real)

Best Regards
Fahmy

Is it possible in set and reset by one clock edge? how is it described in .lib format?

 

[shelby]

... tool doesn't see a path from set to reset. It sees to paths that are racing together one from the clock driving the combinational logic to the set and the other is from the same clock to the reset .

If the timing check is between the set and reset pin on the same flop, then the tool sees and 'arc' between these two pins. This arc is defined in the .lib and can cause violations as you described. If this is truely the case, then you can disable the timing arc defined in the .lib with the set_disable_timing as I mentioned.

 

[muhammadbenali]

try set_multicycle_path between the set and reset signals and vice-versa

 

[Fahmy]

Shelby was right. The following commands fixes the issue

set_disable_timing -from SET -to RESET [get_lib_cell FLOP*]
set_disable_timing -from RESET -to SET [get_lib_cell FLOP*]


I used set false_path instead of them and they didn't work in Encounter .