[STA] PLL -> how should constrained during STA checks?

[ivlsi]

Hello All,

How should PLL (digital or lib of analog one) be constrained during STA checks?

Thank you!

 

[ivlsi]

Are there any comments/response? Please post!

 

[ivlsi]

Re: [STA] PLL -> how should constrained during STA checks?

Any comments?

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PLL jitter is modeled using clock uncertainty. Thank you!

 

[dftrtl]

Re: [STA] PLL -> how should constrained during STA checks?

Yes you should model PLL jitter as uncertainity

 

[mr_vasanth]

Re: [STA] PLL -> how should constrained during STA checks?

I think the real STA will start from the output clock of the PLL. That is the point we define our source clock (main clock) of the design. As other boarders said, PLL characteristics like jitter should be accounted in STA using the command set_clock_uncertainity.