[STA] Hold violation doubt

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maulin sheth

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Hello All,

Suppose ff1 is -> +ve edge clock
ff2 is -> -ve edge clock

ff1/q connected to ff2/input. and clock are same. Just first one is +ve edge triggered and 2nd one is -ve edge triggered flop.

Now,
My doubt is -> why we can not load ff1 and ff2 in the single clock cycle?
We are using lock up latch for this purpose only (we can not load two data in single pulse).

Thanks & Regards,
Maulin
 

Not sure if i understand well.
I think you can load the flops, this is a case of a half cycle path. Did i not understand your question correctly.

On positive edge launch clock and on negative edge the capture clock. Until and unless the setup is too tight to meet this path will violate.

You can manage it clock skew, but need to be careful else your hold will also become tight to manage.
 

Yes. You understand correctly.
I want to know this as you said that we can load the flops, this is the case of a half cycle path.

So if we can load two consecutive flops in single cycle, thn how hold violation occur. Another doubt is that : We are loading two data on two different different consecutive flops, so why hold violation in Scan path...as we have to add lock up latch.

Please help me to clearify my doubt.

Thanks & Regards,
Maulin
 

In this case the hold is already met, as the hold in this case will be checked with the earlier falling edge.
The hold for this would violate if the clock skew is very high in which case the edges would shift.

I was more thinking from the perspective of functional timing path, although i think in scan path as well the reason for hold violation would be same.
 

Yea..That's true..
I think that in case of scan path, there is very less prorogation delay...and the may be skew is high...as there is not any combo logic between launch and capture flop for specifically scan path...That might be the reason for Lock Up Latch...
 

If you are a physical design engineer, you may consider to reorder the scan chains to get the minimum skew between the flops.
 

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