STA --> Constraining IOs for High Speed Serial Interface (HSI)

[Esteban13]

Hi;

could you please help me understanding how to define STA constraints on IOs for an HSI interface ?
What are the important path to checks; especially for the receiving part ?

Thank you in advance

Regards

 

[Adam.Yakuvitz]

Esteban,
You can set up set_input_delay and set_output_delays for your synthesis tools. For Highspeed designs, setting max/min values have had best results . . .

# Constrain the input I/O path
set_input_delay -clock clk -max 3 [all_inputs]
set_input_delay -clock clk -min 2 [all_inputs]

# Constrain the output I/O path
set_output_delay -clock clk 2 [all_outputs] 2

However, you may need to experiment with these . .

-- adam

 

[Esteban13]

Adam;

many thanks for your answer.
BtW; my question was more interface oriented.
My point was to better understand what are the importants parts to check linked to an HSI interface.

Best Regards