As for the SDF file, which designers get from the Layout team and run STA checks on their modules, is it a common for all the chip. I mean, should each designer take a big SDF file for the whole chip for just running STA checks on its small module?
Could the full-chip SDF be divided to the smaller parts, so each designer will back annotate only gates and nets from the module on which he/she run STA checks?
whole chip sdf is a must, i think.
a) if you only checked submodules, how about the interface between the modules.
b) did you take a look at the final layout netlist? it changed a lot, some high fanout pins, clk trees ,some pass through buffers and etc.
how to deal with that.