STA & Async paths

[ivlsi]

Hi All,

The STA tools cannot check the async paths... So, what's the approach? Running Gate-Level simulations?

Thank you!

 

[oratie]

STA can check asynch path: set_max_delay as example.

 

[Shankhy]

There are two types of timing analysis: Static Timing analysis and Dynamic Timing Analysis. Since STA will validate all timing paths in the designs under worst case conditions, at the same time it can't check the logical functionality of the design..so in this case dynamic timing analysis comes into picture which uses simulation vectors to verify that the circuit computes accurate results from a given input without any timing violations...So definitely running gate level simulations will help in checking the async paths...

 

[kannanunni]

STA tools will report async path violations(recovery and removal) and we can specify delay in async path with the command in ETS set_max_delay (with respect to clock edge).