STA aspect: What will be the impact design if we make to much tight transition time.

[mepriyasingh]

STA aspect: What will be impact on design if we make to much tight transition time.

As per STA aspect: What will be the impact on design if we make to much tight transition time. what prime time will do..

 

[morris_mano]

If you have tight transition time during synthesis, may be fanout will be reduced.

 

[mepriyasingh]

If you have tight transition time during synthesis, may be fanout will be reduced.

Thanks
Can you elaborate this so that i am able to understand better.
Can any body else please.

Thanks in Advance

 

[ads-ee]

Thanks
Can you elaborate this so that i am able to understand better.
Can any body else please.

Thanks in Advance

fanout = number of loads on a net.

therefore...
more loads = slower signal transitions
less loads = faster signal transitions

 

[skrishneogg]

Re: STA aspect: What will be impact on design if we make to much tight transition tim

As per STA aspect: What will be the impact on design if we make to much tight transition time. what prime time will do..

If you over constrain max_transition for signals,

1. Buffer counts will increase to meet the constraint
2. Cells will be faster but delay due to buffers will add up much higher
3. Congestion due to increased buffer counts
4. OCV impact will be high if you increase in the number of buffers in clock tree. Increase in #buffers in clock tree --> more OCV --> higher skew. [ OCV: On Chip Variation ]

 

[kumar_eee]

The Power consumption also will go up.