SSTL VIH(ac) levels according to DDR3 SDRAM

Status
Not open for further replies.

Razob

Newbie level 2
Joined
Nov 22, 2009
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,293
Hello, everybody!
I have some misunderstanding about VIH(ac)\VIL(ac) SSTL levels.
Timing specification for DDR3-1066 SDRAM normalized by this levels, for example data setup time tDS is 25ps@AC175 and 90ps@AC135.
Which one of all levels I should use in my timing budget calculation?
Levels are determined by configuring the controller? or they are fixed for specific controller or SDRAM?
Hope for you help)
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…