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SSTL VIH(ac) levels according to DDR3 SDRAM

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Razob

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Hello, everybody!
I have some misunderstanding about VIH(ac)\VIL(ac) SSTL levels.
Timing specification for DDR3-1066 SDRAM normalized by this levels, for example data setup time tDS is 25ps@AC175 and 90ps@AC135.
Which one of all levels I should use in my timing budget calculation?
Levels are determined by configuring the controller? or they are fixed for specific controller or SDRAM?
Hope for you help)
 

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