Non AMP

SSB demodulation .. pls help

Thread starter Taiku
Start date Mar 16, 2004

Status: Not open for further replies.

Mar 16, 2004

#1

T

Taiku

Newbie level 2

Hello I am searching for a SSB (single sideband ) Demodulation routine or core or whatever in VHDL!!!

pls answers if u know something

Status: Not open for further replies.

Similar threads

C
need help with verilog coding a morse code to ascii decoder
- Started by combat5
- May 28, 2024
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design
Microchip FPGA : Need help in some PCIe Throughput calc
- Started by dpaul
- Sep 14, 2023
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design
E
[SOLVED] Please help for Data transferring between Verilog Modules
- Started by EDA_hg81
- Aug 12, 2023
- Replies: 0
PLD, SPLD, GAL, CPLD, FPGA Design
C
Seeking Help with VHDL Timing Issue in Arithmetic Operation
- Started by chandra1502
- Aug 29, 2023
- Replies: 8
PLD, SPLD, GAL, CPLD, FPGA Design
S
TEST BENCH MODIFICATION HELP
- Started by Soh_bhat
- Apr 2, 2023
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design