SRAM write timing request

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john7796

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Hi all,

As we know, due to large RC time constant of SRAM bit line, so it need sense amplifier for read mechanics.
Because the read bit line and write bit line is the same line of SRAM, so their RC time constant is the same.
How could write timing can fast as read timing?

Please help to answer question.

Thanks a lot.
 

Write operation
1. doesn't need the sense amplifier
2. uses a higher voltage than the read operation
 
Hi Erikl,

So if the cell operation voltage is 1.8V in 0.18 um process, the write amplifier maybe will output to 9.0V ~ -9.0V ?

Thanks a lot.
 

john7796 said:
... the write amplifier maybe will output to 9.0V ~ -9.0V ?
Click to expand...

No, sorry: I mixed that up with an EEPROM write operation. SRAM write and read operations use the same voltage.

So just the fact that there is no sense amplifier delay is responsible for a faster write operation.
 

Hi Erikl,

Then the question returns to original point. Their RC time constant is the same.
However the write voltage is full swing, and the read voltage is small swing. How could write timing can fast as read timing?
 

Hi John,

the data sheets of SRAMs - which I found - show - resp: guarantee - all the same read and write times. Which SRAM did you find with faster write times?

Both the read and the write operation need data buffering (reading data from an SRAM doesn't actually need a sense amplifier - this is just necessary for DRAMs), but the read buffer probably needs some amplification. So the only reason I could imagine are faster buffers for the write than for the read operation.
 

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