SRAM Understanding

Hi Folks,

I am new to the Microcontrollers and understanding FMC interfacing (Ram) to Microcontroller.
I have selected 512k (32k x 16) ram.

in the block diagram.. i understood the meaning 16 which is nothing but width of Data.

Here i can see 15 address lines (A0-A14).. I dont know why? what is the rational of using
and it is done as ROW Decoder (A0-A7) and Column decoder (A8-A14).. i did not understand it.

Can someone help me to understand the Basic behind this.

Regards,
Samuel

Hi,

Imagine each memory cell as a box.
Lets say you have 32 boxes.
Now put the 32 boxes on the floor an place them next to each other.
Now you can use 4 rows with 8 boxes each ( giving 32 in total)
For the 4 rows you need 2 binary signals (address lines) to be decoded ( 2^2 = 4)
For the 8 columns you need 3 signals (2^3=8)

****
In the end it does not matter how your SRAM cells are arranged: for 32k cells you need 15 address lines. 2^15 = 32768 = 32k

Klaus

Hi Klaus.
Great.. convinced.

Hi Klaus,
I was checking few datasheets where i have observed BHE(Byte High Enable) and BLE(Byte Low Enable)..

What is the purpose of those? why we need those.. If we want to read or write data we can read all 16bits (D0-D15)

Samuel.

I can't remember seeing those terms in memory specifications but they are quite common when referring to large scale processors.

Basically, in some instances it is cheaper or more convenient to use memories that have a smaller data width than the processor. For example using 8-bit memories on 16-bit, 32-bit or 64-bit systems. The byte enables allow larger values to be sent down a narrower data bus by dividing it into smaller widths (nybles). To allow say a 16-bit value to be stored at a memory address it might require two 8-bit memories, one for the lower eight bits and one for the higher eight bits but both can be at the same address. The processor sets up the appropriate address then enables one of the two byte enables so only one of the memories is activated, it can then transfer the data to or from that device, it then deactivate that enable, activates the other one and writes/reads the other half of the data bus. The BHE/BLE signals are steering the data to the appropriate memory so each address seems wider than the external data bus pins could otherwise carry.

Brian.

KlausST said:

Hi,

Imagine each memory cell as a box.
Lets say you have 32 boxes.
Now put the 32 boxes on the floor an place them next to each other.
Now you can use 4 rows with 8 boxes each ( giving 32 in total)
For the 4 rows you need 2 binary signals (address lines) to be decoded ( 2^2 = 4)
For the 8 columns you need 3 signals (2^3=8)

****
In the end it does not matter how your SRAM cells are arranged: for 32k cells you need 15 address lines. 2^15 = 32768 = 32k

Klaus

Click to expand...

Hi Klaus,
How much Data bus width required to access each memory locations?
How it is defined..?

Let's say I put address of 10000 on the address bus.. now to read/write particular location how much Data bus width required?
What is the mechanism to decide?

Hi

Data bus with does not matter.
You may have 1, 8, 32, ....13 or any other value.

Back to the boxes:
For 32 boxes you need 5 lines, independent how many eggs are in each box.

Klaus

The data bus width depends entirely on the design of the processor, there is no particular reason why any size can't be used but some sizes are more useful than others. Small data buses generally require more accesses to do tasks but ones too big will waste bits that rarely get used. MCUs started with 4 bit data buses, that size being chosen because it could hold all the decimal digits from zero to nine (0000 - 1001) then 8-bit buses came into use because they could also handle enough combinations to carry all the alphabet as well. From then on, they generally doubled in size so that existing memory devices could still be used with appropriate enable signals as you have already seen.

Brian.

KlausST said:

Hi

Data bus with does not matter.
You may have 1, 8, 32, ....13 or any other value.

Back to the boxes:
For 32 boxes you need 5 lines, independent how many eggs are in each box.

Klaus

Click to expand...

Hi Klaus,
I have seen address line seperate and Data lines seperate.

I understood the concept of Address lines-which only point out the particular address from memory locations to read/Write and it is unidirectional.

Now if I want to read/write some data on the particular memory location which is specified by address bus..
I need to have some datalines (Bidirectional) where I can put some data to read/write.

How much datalines is required..?

In above examples of cypress.. they have 16 Datalines(IO0-IO15) and 16Address lines (A0-A15)..

Hi,

Bjtpower said:

How much datalines is required..?

Click to expand...

We don't know. If you don't know...nobody else can know.

We don't know what data you want to store, where they come from. We don't know which ICs you use.

...
It's like:
You want "something" store in a box...and ask us about the size of the box. But we don't know what "something" is.
Thus we can't know how big it is.

Klaus