SRAM TIMING WAVEFORM

[im_pam]

Hi,

i have one query related to the SRAM timing diagram. can anyone please tell me where do we give the input of the clock that is shown in the reference image.

how do we decide when it is read cycle and when it is write cycle .

(Image for reference only).

thank you

 

[ThisIsNotSam]

It looks like WBL and RBL and complementary signals and they decide when you are reading writing. But who knows, I don't know what this memory is supposed to do and where you got it from.

 

[im_pam]

it is not about what wbl and RBL , my main concern is where CLK signal input is given , forget about 1st image. in second image also CLK signal is given. i have shared another image for reference.

 

[BradtheRad]

A lone memory cell (a bit) theoretically needs no clock pulse. Thus it can be a simple RS flip-flop.

In practice memory cells are in groups of 8 bits, making a byte. It's necessary to keep all 8 actions synchronized (Read and Write). To perform these simultaneously, the 8 flip-flops are a kind which all obey the same clock pulse to the clock pin.

 

[im_pam]

@BradtheRad well , being a beginner i have taken 16*8 array sram . for that i need clock and i am confused for this. and and i am using 6T sram array for that.

 

[ThisIsNotSam]

it is not about what wbl and RBL , my main concern is where CLK signal input is given , forget about 1st image. in second image also CLK signal is given. i have shared another image for reference.

can't you trace the clk and see where it arrives?

 

[dick_freebird]

In my ancient experience with SRAMs the "clock" is generated by logic
from address transition detectors (along with any CE and R/Wb changes).

But DDRx SRAMs might have more "serial stuff" and the high speed
lines maybe do have an explicit clock. I have never had occasion to peel
back the lid on that.

 

[FvM]

SRAM doesn't use a clock. Imagine that the clock in the timing diagram is used to generate the control signals of the test setup.

 

[im_pam]

@FvM you mean generation of Write enable clock , read enable clock etc ??

 

[FvM]

Don't know what you specifically mean with write or read enable clock. I mean all control signals driving the circuit - all signals except for RBL which is an output generated by the RAM.

 

[im_pam]

@FvM i am talking about the Enable clock given to the row decoder and one clock given to the write drive

 

[FvM]

Yes, WWL and RWL are obviously derived from the clock, but also write data WBL, WBLB and enable signals FTRW and FTRR.

 

[im_pam]

Alright , i am facing problem with multiple word line , Suppose i write data in 1 column 1 row after that write enable will be low and WL0 will also be low , now what is next. . If i want to read 1cl 1 row data, i have to make WL0 high . but how it will be done

i have attached an image for reference .

 

[FvM]

The read condition is RWLx = 1 and FTRRx = 0. You'll have decoders for binary row and column addresses to generate the signals.