SRAM Peripherals

[im_pam]

Hi
the sram read and write operation is only performed when enable is high or not ?
in this sram array circuit, they have not used row enable. is CE (chip enable ) here working same as row enable [ left bottom corner of the image shown ].

thanks

 

[FvM]

Don't think that the diagram has much to do with actual transistor level implementation.

 

[KlausST]

Hi,

the sram read and write operation is only performed when enable is high or not ?

The pictrure shows 3 "enable" signals:
* CE: chip enable. Always needed for R and W access. It wakes up the internal circuitry (low power sleep vs active)
* WE: write enable. Used to tell tha chip that you want to store data into the SRAM
* OE: output enable. Usec to drive the data (bus) lines. High-Z vs Output. High-Z so that other devices can drive the data lines.

Klaus

 

[im_pam]

than you for the response @KlausST, if CE is performing the wake up operation then what does enable signal do in the ROW decoder?

 

[KlausST]

what does enable signal do in the ROW decoder

Look at your picture. There is no enable input to the row decoder.

Klaus