SRAM-Parallel-Async DualPort versus Standard - request for clarification

[FlyingDutch]

Hello,

I can't find differences between two SRAM Async memories (parallel) in their interface. In FPGA IpCores "Dual Port" RAM memories has two separate address and data ports. Could somebody explain me why these two example SRAM ICs are described as "Dual Port" or not. The first SRAM IC - "IS61WV102416FBLL-10T2LI-TR-ND" is desribed on Digi-Key web page as "Dual port" - see links:

https://www.digikey.pl/product-deta...T2LI-TR/IS61WV102416FBLL-10T2LI-TR-ND/8563776

http://www.issi.com/WW/pdf/61-64WV102416FALL-BLL.pdf

The second SRAM IC - "IS61WV204816BLL-10TLI " is not described as "Dual port" - see links:

https://www.digikey.pl/products/en/...Sort=0&page=1&stock=1&datasheet=1&pageSize=25

https://www.issi.com/WW/pdf/61-64WV204816BLL.pdf

When I am looking in their datasheets I can't find differences in address and data busses (the first IC hasn't two separate addres and data ports). Could somebody explain me why this first IC is described as "Dual Port" ?

Thanks in advance and Regards

 

[KlausST]

Hi,

the datasheet of IS61WV102416FBLL-10T2LI-TR-ND does not mention "dual port".
--> a digikey description mistake.

I didn´t go deeply through the datsheets. But I expect there is a difference in memory size, thus there should be a difference in address line count.

Klaus

 

[FlyingDutch]

Hi,

the datasheet of IS61WV102416FBLL-10T2LI-TR-ND does not mention "dual port".
--> a digikey description mistake.

I didn´t go deeply through the datsheets. But I expect there is a difference in memory size, thus there should be a difference in address line count.

Klaus

Hello Klaus,

It is still unclear for me. I thought that "Dual Port" interface require two separate addres and data buses in order to one can read from one addres and write for second addres in the same time. How to achieve such action with one of these memory ICs?

BTW: so as I understood you correctly - none of these memory ICs is "Dual Port". If yes could you point me real "Dual Port" memory IC (link to description)?

Best Regards

 

[FvM]

I thought that "Dual Port" interface require two separate addres and data buses in order to one can read from one addres and write for second addres in the same time.

That'show it is. The first article is a regular single port asynchronous RAM with an erroneous description in the Digikey catalog. Digikey has however a number of asynchronous and synchronous dual port RAM in the portfolio.

For your intended application (FPGA interface), it's generally simpler to use synchronous RAM. Unfortunately they are less commonly used and respectively more expensive.

 

[FlyingDutch]

That's how it is. The first article is a regular single port asynchronous RAM with an erroneous description in the Digikey catalog. Digikey has however a number of asynchronous and synchronous dual port RAM in the portfolio.

For your intended application (FPGA interface), it's generally simpler to use synchronous RAM. Unfortunately they are less commonly used and respectively more expensive.

Hello,

yes I found synchronous RAM in Digi-Key offer, but prices around 500$ are not for amateur circuits

Could someone point me (link) real "Dual Port" example asynchronous SRAM (Parallel interface) ?

Best Regards

 

[FvM]

You can simply find it by selecting asynchronous dual port SRAM in the Digikey part search. E.g. https://www.cypress.com/file/138686/download

 

[KlausST]

Hi,

you can do a selection on "SRAM-Dual port" in Digikey.
Maybe there are some description errors. But don´t focus on those 5% or so.
Focus on the devices where the first page of the datasheet says "dual port".

Klaus

--- Updated Oct 31, 2020 ---

Hi,

but prices around 500$ are not for amateur circuits

Dual port are expensive.
Do you really need dual port?
I've done CPLD / FPGA designs wher a ADC, a DAC and a microcontroller share the same SRAM. Fast SRAM, single port.
It´s fast enough to handle the accesses without drawback.
O.K. A bit of reading datasheets and writing CPLD/FPGA code is necessary...

Klaus

 

[FlyingDutch]

Hi,

Dual port are expensive.
Do you really need dual port?
I've done CPLD / FPGA designs wher a ADC, a DAC and a microcontroller share the same SRAM. Fast SRAM, single port.
It´s fast enough to handle the accesses without drawback.
O.K. A bit of reading datasheets and writing CPLD/FPGA code is necessary...

Klaus

Hi,

not, but it can help to design fast frame-buffer (min 30 fps) for full HD resolution camera (as external circuit for connection to FPGA board).

Best Regards

 

[KlausST]

Hi,

OK, just an idea - don´t know if is possible...

you may use two cheap standard SRAMs. Each address bus and data bus is independently controlled by the FPGA.
So the FPGA can decide (according frame rate) to write into SRAM A... while you are able to process the data of SRAM B
for the next frame the FPGA switches the SRAMs, ..
...to write into SRAM B... while you process the data of SRAM A

Klaus

 

[FlyingDutch]

Hi, yes it is worth doing (I thought about it - I probably implement it in my second trial).

Best Regards