jemmy
Junior Member level 1
sram simulation
Can anybody introduce me how to do the following 6-T SRAM bit cell analysis with Hspice:
1.Standby current on VDD;
2.Read and Write Margin;
3.bit-lin leakage
I have tried to simulate the standby current on VDD. I set BL,BL_ and WL to 0, and also using ic(Q)=1.8v(I simulate with 018u logic process model card). I find i(VDD) is very close to zero, but not a constant. Sometimes it is nagative, and sometimes it is positive number. I don't know why. I'm a beginer on SRAM and Hspice. I'm not sure whether this way is correct.
Attached pic is the sram schematic.
Thanks for your help.
Can anybody introduce me how to do the following 6-T SRAM bit cell analysis with Hspice:
1.Standby current on VDD;
2.Read and Write Margin;
3.bit-lin leakage
I have tried to simulate the standby current on VDD. I set BL,BL_ and WL to 0, and also using ic(Q)=1.8v(I simulate with 018u logic process model card). I find i(VDD) is very close to zero, but not a constant. Sometimes it is nagative, and sometimes it is positive number. I don't know why. I'm a beginer on SRAM and Hspice. I'm not sure whether this way is correct.
Attached pic is the sram schematic.
Thanks for your help.